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two selectable inputs, 8 lvpecl outputs, sige clock fanout buffer ADCLK948 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2010 analog devices, inc. all rights reserved. features features 2 selectable differential inputs 2 selectable differential inputs 4.8 ghz operating frequency 4.8 ghz operating frequency 75 fs rms broadband random jitter 75 fs rms broadband random jitter on-chip input terminations on-chip input terminations 3.3 v power supply 3.3 v power supply applications applications low jitter clock distribution low jitter clock distribution clock and data signal restoration clock and data signal restoration level translation level translation wireless communications wireless communications wired communications wired communications medical and industrial imaging medical and industrial imaging ate and high performance instrumentation ate and high performance instrumentation general description general description the ADCLK948 is an ultrafast clock fanout buffer fabricated on the analog devices, inc., proprietary xfcb3 silicon germanium (sige) bipolar process. this device is designed for high speed applications requiring low jitter. the ADCLK948 is an ultrafast clock fanout buffer fabricated on the analog devices, inc., proprietary xfcb3 silicon germanium (sige) bipolar process. this device is designed for high speed applications requiring low jitter. the device has two selectable differential inputs via the in_sel control pin. both inputs are equipped with center tapped, differential, 100 on-chip termination resistors. the inputs accept dc-coupled lvpecl, cml, 3.3 v cmos (single-ended), and ac-coupled 1.8 v cmos, lvds, and lvpecl inputs. a v ref x pin is available for biasing ac-coupled inputs. the device has two selectable differential inputs via the in_sel control pin. both inputs are equipped with center tapped, differential, 100 on-chip termination resistors. the inputs accept dc-coupled lvpecl, cml, 3.3 v cmos (single-ended), and ac-coupled 1.8 v cmos, lvds, and lvpecl inputs. a v ref x pin is available for biasing ac-coupled inputs. the ADCLK948 features eight full-swing emitter coupled logic (ecl) output drivers. for lvpecl (positive ecl) operation, bias v cc to the positive supply and v ee to ground. for ecl operation, bias v cc to ground and v ee to the negative supply. the ADCLK948 features eight full-swing emitter coupled logic (ecl) output drivers. for lvpecl (positive ecl) operation, bias v cc to the positive supply and v ee to ground. for ecl operation, bias v cc to ground and v ee to the negative supply. the output stages are designed to directly drive 800 mv each side into 50 terminated to v cc ? 2 v for a total differential output swing of 1.6 v. the output stages are designed to directly drive 800 mv each side into 50 terminated to v cc ? 2 v for a total differential output swing of 1.6 v. the ADCLK948 is available in a 32-lead lfcsp and specified for operation over the standard industrial temperature range of ?40c to +85c. the ADCLK948 is available in a 32-lead lfcsp and specified for operation over the standard industrial temperature range of ?40c to +85c. functional block diagram functional block diagram q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 q5 q5 q6 q6 q7 q7 v t 0 v ref 0 v ref 1 in_sel clk0 clk0 v t 1 clk1 clk1 lvpecl ADCLK948 reference reference 08280-001 figure 1.
ADCLK948 rev. a | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 absolute maximum ratings ............................................................ 5 determining junction temperature .......................................... 5 esd caution .................................................................................. 5 thermal performance .................................................................. 5 pin configuration and function descriptions ..............................6 typical performance characteristics ..............................................7 functional description .....................................................................9 clock inputs ...................................................................................9 clock outputs ................................................................................9 clock input select (in_sel) settings...................................... 10 pcb layout considerations ...................................................... 10 input termination options ....................................................... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 6/10rev. 0 to rev. a changed output voltage differential parameter to output voltage, single ended parameter, table 1 ..................................... 3 changes to output voltage, single ended parameter, table 1 ... 3 7/09revision 0: initial version
ADCLK948 rev. a | page 3 of 12 specifications electrical characteristics typical (typ column) values are given for v cc ? v ee = 3.3 v and t a = 25c, unless otherwise noted. minimum (min column) and maximum (max column) values are given over the full v cc ? v ee = 3.3 v 10% and t a = ?40c to +85c variation, unless otherwise noted. table 1. clock inputs and outputs parameter symbol min typ max unit test conditions/comments dc input characteristics input common mode voltage v icm v ee + 1.5 v cc ? 0.1 v input differential range v id 0.4 3.4 v p-p 1.7 v between input pins input capacitance c in 0.4 pf input resistance single-ended mode 50 differential mode 100 common mode 50 k open v t x input bias current 20 a hysteresis 10 mv dc output characteristics output voltage high level v oh v cc ? 1.26 v cc ? 0.76 v 50 to (v cc ? 2.0 v) output voltage low level v ol v cc ? 1.99 v cc ? 1.54 v 50 to (v cc ? 2.0 v) output voltage, single ended v o 610 960 mv v oh ? v ol , output static reference voltage v ref output voltage (v cc + 1)/2 v ?500 a to +500 a output resistance 235 table 2. timing characteristics parameter symbol min typ max unit test conditions/comments ac performance maximum output frequency 4.5 4.8 ghz see figure 4 for differential output voltage vs. frequency, >0.8 v differential output swing output rise time t r 40 75 90 ps 20% to 80% measured differentially output fall time t f 40 75 90 ps propagation delay t pd 175 210 245 ps v icm = 2 v, v id = 1.6 v p-p temperature coefficient 50 fs/c output-to-output skew 1 9 25 ps part-to-part skew 45 ps v id = 1.6 v p-p additive time jitter integrated random jitter 28 fs rms bw = 12 khz ? 20 mhz, clk = 1 ghz broadband random jitter 2 75 fs rms v id = 1.6 v p-p, 8 v/ns, v icm = 2 v crosstalk-induced jitter 3 90 fs rms clock output phase noise absolute phase noise input slew rate > 1 v/ns (see figure 11 , the phase noise plot, for more details) f in = 1 ghz ?119 dbc/hz @100 hz offset ?134 dbc/hz @1 khz offset ?145 dbc/hz @10 khz offset ?150 dbc/hz @100 khz offset ?150 dbc/hz >1 mhz offset 1 the output skew is the difference betw een any two similar delay paths while operat ing at the same voltage and temperature. 2 measured at the rising edge of the clock signal; calculated using the snr of the adc method. 3 this is the amount of added jitter measured at the output whil e two related, asynchronous, diff erential frequencies are applie d to the inputs.
ADCLK948 rev. a | page 4 of 12 table 3. input select control pin parameter symbol min typ max unit logic 1 voltage v ih v cc ? 0.4 v cc v logic 0 voltage v il v ee 1 v logic 1 current i ih 100 a logic 0 current i il 0.6 ma capacitance 2 pf table 4. power parameter symbol min typ max unit test conditions/comments power supply supply voltage requirement v cc ? v ee 2.97 3.63 v 3.3 v + 10% power supply current static negative supply current i vee 96 120 ma v cc ? v ee = 3.3 v 10% positive supply current i vcc 288 330 ma v cc ? v ee = 3.3 v 10% power supply rejection 1 psr vcc <3 ps/v v cc ? v ee = 3.3 v 10% output swing supply rejection 2 psr vcc 28 db v cc ? v ee = 3.3 v 10% 1 change in t pd per change in v cc . 2 change in output sw ing per change in v cc .
ADCLK948 rev. a | page 5 of 12 absolute maximum ratings table 5. parameter rating supply voltage v cc ? v ee 6 v input voltage clk0, clk1, clk0 , clk1 , in_sel v ee ? 0.5 v to v cc + 0.5 v clk0, clk1, clk0 , clk1 to v t x pin (cml, lvpecl termination) 40 ma clk0, clk1 to clk0 , clk1 1.8 v input termination, v t x to clk0, clk1, clk0 , and clk1 2 v maximum voltage on output pins v cc + 0.5 v maximum output current 35 ma voltage reference (v ref x) v cc to v ee operating temperature range ambient ?40c to +85c junction 150c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. determining junction temperature to determine the junction temperature on the application printed circuit board (pcb), use the following equation: t j = t case + ( jt p d ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the customer at the top center of the package. jt is from tabl e 6 . p d is the power dissipation. va lu e s of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approxi- mation of t j by the equation t j = t a + ( ja p d ) where t a is the ambient temperature (c). va lu e s of jb are provided in table 6 for package comparison and pcb design considerations. esd caution thermal performance table 6. parameter symbol description value 1 unit junction-to-ambient thermal resistance ja still air per jedec jesd51-2 0 m/sec air flow 49.8 c/w moving air jma per jedec jesd51-6 1 m/sec air flow 43.5 c/w 2.5 m/sec air flow 39.0 c/w junction-to-board thermal resistance jb moving air per jedec jesd51-8 1 m/sec air flow 30.7 c/w junction-to-case thermal resistance jc moving air per mil-std 883, method 1012.1 die-to-heatsink 8.8 c/w junction-to-top-of-package characterization parameter jt still air per jedec jesd51-2 0 m/sec air flow 0.7 c/w 1 results are from simulations. the pcb is a jedec multilayer ty pe. thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations.
ADCLK948 rev. a | page 6 of 12 pin configuration and fu nction descriptions notes 1. nc = no connect. 2 . epad must be soldered to v ee power plane. pin 1 indicator 1 clk0 2 clk0 3 v ref 0 4v t 0 5 clk1 6 clk1 7v t 1 8 v ref 1 24 q2 23 q2 22 q3 21 q3 20 q4 19 q4 18 q5 17 q5 9 n c 1 0 v c c 1 1 q 7 1 2 q 7 1 3 q 6 1 4 q 6 1 5 v c c 1 6 v c c 3 2 i n _ s e l 3 1 v c c 3 0 q 0 2 9 q 0 2 8 q 1 2 7 q 1 2 6 v c c 2 5 v c c top view (not to scale) ADCLK948 0 8280-002 figure 2. pin configuration table 7. pin function descriptions pin no. mnemonic description 1 clk0 differential input (positive) 0. 2 clk0 differential input (negative) 0. 3 v ref 0 reference voltage. reference voltage for biasing ac-coupled clk0 and clk0 inputs. 4 v t 0 center tap. center tap of a 100 input resistor for clk0 and clk0 inputs. 5 clk1 differential input (positive) 1. 6 clk1 differential input (negative) 1. 7 v t 1 center tap. center tap of a 100 input resistor for clk1 and clk1 inputs. 8 v ref 1 reference voltage. reference voltage for biasing ac-coupled clk1 and clk1 inputs. 9 nc no connection. 10, 15, 16, 25, 26, 31 v cc positive supply pin. 11, 12 q7 , q7 differential lvpecl outputs. 13, 14 q6 , q6 differential lvpecl outputs. 17, 18 q5 , q5 differential lvpecl outputs. 19, 20 q4 , q4 differential lvpecl outputs. 21, 22 q3 , q3 differential lvpecl outputs. 23, 24 q2 , q2 differential lvpecl outputs. 27, 28 q1 , q1 differential lvpecl outputs. 29, 30 q0 , q0 differential lvpecl outputs. 32 in_sel input select. logic 0 selects clk0 and clk0 inputs. logic 1 selects clk1 and clk1 inputs. epad the exposed pad (epad) must be connected to v ee .
ADCLK948 rev. a | page 7 of 12 typical performance characteristics v cc = 3.3 v, v ee = 0 v, v icm = v ref x , t a = 25c, clock outputs terminated at 50 to v cc ? 2 v, unless otherwise noted. c3 c4 c3 100mv/div 500ps/div 08280-003 figure 3. lvpecl output waveform @ 200 mhz 1.8 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0 1000 2000 3000 4000 5000 differential output voltage (v) frequency (mhz) 08280-004 figure 4. differential output voltage vs. frequency, v id > 1.1 v p-p 225 180 185 190 195 200 205 210 215 220 01 1.61.41.21.00.80.60.40.2 propagation delay (ps) differential input voltage swing (v) . 8 08280-005 figure 5. propagation delay vs. differential input voltage c4 c3 c4 100mv/div 100ps/div 08280-006 figure 6. lvpecl output waveform @ 1000 mhz 214 213 212 211 210 209 208 207 ?40 80 60 40 20 0 ?20 propagation delay (ps) temperature (c) 08280-007 figure 7. propagation delay vs. temperature, v id = 1.6 v p-p 230 190 200 210 220 0.9 3.12.92.72.52.32.11.91.7 1.51.31.1 propagation delay (ps) dc common-mode voltage (v) +85c +25c ?40c 08280-008 figure 8. propagation delay vs. dc common-mode voltage vs. temperature, input slew rate > 25 v/ns
ADCLK948 rev. a | page 8 of 12 1.56 1.54 1.52 1.50 1.48 1.46 1.44 1.42 2.75 2.85 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75 differential output voltage swing (v) power supply (v) +85c +25c ?40c 08280-009 figure 9. differential output voltage swing vs. power supply voltage vs. temperature, v id = 1.6 v p-p 08280-010 350 300 250 200 150 100 50 0 2.75 3.75 3.50 3.25 3.00 supply current (ma) supply voltage (v) icc iee +85c +25c ?40c figure 10. power supply current vs. powe r supply voltage vs. temperature, all outputs loaded (50 to v cc ? 2 v). ? 90 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 10 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) clock source ADCLK948 absolute phase noise measured @ 1ghz with agilent e5052 using wenzel clock source consisting of a wenzel 100mhz crystal oscillator (p/n 500-06672), wenzel 5 multiplier (p/n lnom-100-5-13-14-f-a), and a wenzel 2 multiplier (p/n lndd-500-14-14-1-d). 08280-011 figure 11. absolute phase noise measured @1 ghz 300 250 200 150 100 50 0 02 20 15 10 5 random jitter (f s rms) input slew rate (v/ns) 5 08280-012 figure 12. rms random jitter vs. input slew rate, v id method
ADCLK948 rev. a | page 9 of 12 functional description clock inputs the ADCLK948 accepts a differential clock input from one of two inputs and distributes the selected clock to all eight lvpecl outputs. the maximum specified frequency is the point at which the output voltage swing is 50% of the standard lvpecl swing (see figure 4 ). see the functional block diagram ( figure 1 ) and the general description section for more clock input details. see figure 19 through figure 23 for various clock input termination schemes. output jitter performance is degraded by an input slew rate below 4 v/ns, as shown in figure 12 . the ADCLK948 is specifically designed to minimize added random jitter over a wide input slew rate range. whenever possible, clamp excessively large input signals with fast schottky diodes because attenuators reduce the slew rate. input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics. clock outputs the specified performance necessitates using proper transmission line terminations. the lvpecl outputs of the ADCLK948 are designed to directly drive 800 mv into a 50 cable or into microstrip/stripline transmission lines terminated with 50 referenced to v cc ? 2 v, as shown in figure 14 . the lvpecl output stage is shown in figure 13 . the outputs are designed for best transmission line matching. if high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse width depen- dent propagation delay dispersion. v ee v cc qx qx 08280-013 figure 13. simplified schematic diagram of the lvpecl output stage figure 14 through figure 17 depict various lvpecl output termination schemes. when dc-coupled, v s of the receiving buffer should match vs_drv. thevenin-equivalent termination uses a resistor network to provide 50 termination to a dc voltage that is below v ol of the lvpecl driver. in this case, vs_drv on the ADCLK948 should equal v s of the receiving buffer. although the resistor combination shown (in figure 15 ) results in a dc bias point of vs_drv ? 2 v, the actual common-mode voltage is vs_drv ? 1.3 v because there is additional current flowing from the ADCLK948 lvpecl driver through the pull-down resistor. lvpecl y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. its main drawback is that it offers limited flexibility for varying the drive strength of the emitter follower lvpecl driver. this can be an important consideration when driving long trace lengths but is usually not an issue. v s_drv z 0 = 50 ? v s = vs_dr v lvpecl 50? v cc ? 2v 50? z 0 = 50 ? a dclk948 08280-014 figure 14. dc-coupled, 3.3 v lvpecl vs_drv 50? 50? single-ended (not coupled) v s v s_drv lvpecl 127? 127? 83? 83 ? ADCLK948 0 8280-015 figure 15. dc-coupled, 3.3 v lvpecl far-end thevenin termination vs_drv z 0 = 50 ? v s = vs_drv lvpecl 50? 50 ? 50? z 0 = 50 ? a dclk948 0 8280-016 figure 16. dc-coupled, 3.3 v lvpecl y-termination vs_drv 100 ? differential (coupled) transmission line v s lvpecl 100? 0.1nf 0.1nf 200 ? 200? a dclk948 08280-017 figure 17. ac-coupled, lvpecl with parallel transmission line
ADCLK948 rev. a | page 10 of 12 clock input select (in_sel) settings a logic 0 on the in_sel pin selects the input clk0 and input clk0 . a logic 1 on the in_sel pin selects input clk1 and input clk1 . pcb layout considerations the ADCLK948 buffer is designed for very high speed applica- tions. consequently, high speed design techniques must be used to achieve the specified performance. it is critically important to use low impedance supply planes for both the negative supply (v ee ) and the positive supply (v cc ) planes as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. the following references to the gnd plane assume that the v ee power plane is grounded for lvpecl operation. note that, for ecl operation, the v cc power plane becomes the ground plane. it is also important to adequately bypass the input and output supplies. place a 1 f electrolytic bypass capacitor within several inches of each v cc power supply pin to the gnd plane. in addition, place multiple high quality 0.001 f bypass capacitors as close as possible to each of the v cc supply pins, and connect the capacitors to the gnd plane with redundant vias. carefully select high frequency bypass capacitors for minimum induc- tance and esr. to improve the effectiveness of the bypass at high frequencies, minimize parasitic layout inductance. also, avoid discontinuities along input and output transmission lines that can affect jitter performance. in a 50 environment, input and output matching have a significant impact on performance. the buffer provides internal 50 termination resistors for both clkx and clkx inputs. normally, the return side is connected to the reference pin that is provided. carefully bypass the termination potential using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. if the inputs are dc- coupled to a source, take care to ensure that the pins are within the rated input differential and common-mode ranges. if the return is floated, the device exhibits a 100 cross termi- nation, but the source must then control the common-mode voltage and supply the input bias currents. there are esd/clamp diodes between the input pins to prevent the application from developing excessive offsets to the input transistors. esd diodes are not optimized for best ac perfor- mance. when a clamp is required, it is recommended that appropriate external diodes be used. exposed metal paddle the exposed metal paddle on the ADCLK948 package is both an electrical connection and a thermal enhancement. for the device to function properly, the paddle must be properly attached to the v ee power plane. when properly mounted, the ADCLK948 also dissipates heat through its exposed paddle. the pcb acts as a heat sink for the ADCLK948. the pcb attachment must provide a good thermal path to a larger heat dissipation area. this requires a grid of vias from the top layer down to the v ee power plane (see figure 18 ). the ADCLK948 evaluation board (ADCLK948/pcbz) pro- vides an example of how to attach the part to the pcb. vias to v ee power plane 08280-018 figure 18. pcb land for attaching exposed paddle
ADCLK948 rev. a | page 11 of 12 input termination options v ref x v cc v t x clkx clkx connect v t xtov cc . 50? 50? 08280-019 ADCLK948 figure 19. dc-coupled cml input termination v ref x v t x v cc 50? 50 ? clkx clkx 08280-020 0.01f (optional) 50? ADCLK948 figure 20. dc-coupled lvpecl input termination v ref x v t x connect v t xtov ref x. 50? 50? clkx clkx 08280-021 ADCLK948 figure 21. ac-coupled input termin ation, such as lvds and levpecl v ref x v t x c onnect v t x, v ref x, and clkx. place a bypass capacitor from v t x to ground. a lternatively, v t x, v ref x, and clkx can be c onnected, giving a cleaner layout and a 180o phase shift. 50? 50? clkx clkx 08280-022 ADCLK948 figure 22. ac-coupled sing le-ended input termination v ref x v t x 50? 50 ? clkx clkx 08280-023 ADCLK948 figure 23. dc-coupled 3.3 v cmos input termination
ADCLK948 rev. a | page 12 of 12 032807-a compliant to jedec standards mo-220-vhhd-2 outline dimensions 1 32 8 9 25 24 17 16 2.85 2.70 sq 2.55 top view coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.20 min exposed pad (bottom view) pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 24. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADCLK948bcpz ?40c to +85c 32-lead lfcsp_vq cp-32-8 ADCLK948bcpz-reel7 ?40c to +85c 32-lead lfcsp_vq cp-32-8 ADCLK948/pcbz evaluation board 1 z = rohs compliant part. ?2009C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08280-0-6/10(a)

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